1. Field of the Invention
The present invention relates to determining chip resistance model, and more specifically to full-chip resistance extraction.
2. Description of the Related Art
Resistance values of on chip wiring are often used for signal timing and signal noise analysis. For performance reasons, full chip resistance extraction is often based on wire layout geometry. Once a certain layout geometry is encountered, a corresponding resistance model is often reported. In addition, typical parasitic resistance extraction algorithms generally have the relation of layout and resistor model hardcoded. With changing technology and downstream tool requirements, current resistance models are often no longer accurate. Unfortunately, translating models is often difficult to achieve. Thus, resistance determination when layout of wires on a chip are changed can be difficult.
Generally, to obtain a resistance model, a purely mathematical model may be utilized with every change in layout geometry. Unfortunately, usage of mathematical models for every portion of the geometric layout is complex and difficult. Consequently, determining the resistance models for a new chip design can take a lengthy period of time and therefore, can increase the cost of new chip designs.
Consequently, there is a need for a new method where determining resistance models can be accomplished in a less complex and time consuming manner. Accordingly, what is needed is an apparatus and a method for translating layout into resistance models in an accurate and intelligent manner.